This invention relates to the repair of semiconductor memory.
This application claims the benefit of the May 22, 2001 priority date of German application 101 25 028.2-53, the contents of which are herein incorporated by reference.
Semiconductor memory apparatuses which, within certain limits, allow faulty column lines (that is to say data lines or bit lines) to be repaired, are known. For this purpose, the cell array of such a semiconductor memory apparatus contains redundant column lines, which can be used as replacement lines for defective column lines. If a defective column line is found in a test procedure after production of the semiconductor apparatus, then an activation device which is integrated in the semiconductor memory apparatus is activated, in order to replace the defective column line by one of the redundant column lines. Such activation devices normally include a large number of addressing fuses, which are also referred to as column redundancy fuses. Addressing fuses such as these can be xe2x80x9cprogammedxe2x80x9d, for example by applying an electrical voltage or by means of a laser, as function of the electrical address of the faulty column line, by blowing the fuses. A so-called master fuse is normally also programmed, in order to activate the redundant column line.
If access is now made to that memory cell array of the semiconductor memory apparatus whose electrical address has the faulty column line, then a logic gate in the activation device ensures that the redundant column line is addressed instead of the defective column line. A semiconductor memory apparatus which has been repaired in this way behaves, for the user, like a semiconductor memory apparatus which has been fault-free from the start. The use of redundant column lines for repairing defective column lines in conjunction with such an activation device thus allows a greater yield from the production of semiconductor memory apparatuses, since defective column lines can, within certain limits, be repaired.
However, the addressing fuses require a certain amount of surface area on the semiconductor memory apparatus, so that the chip size of such components is larger than that of those without a repair capability. The advantage of a greater yield is thus a trade-off against an increased chip surface area.
One object of the invention is to specify a semiconductor memory apparatus having a column repair capability, which requires only a comparatively small chip size. A further object of the invention is to specify a corresponding repair method for semiconductor memory apparatuses.
According to the invention, these objects are achieved by a semiconductor memory apparatus according to claim 1, and by a repair method for a semiconductor memory apparatus according to claim 11. Preferred embodiments are the subject matter of the dependent claims.
According to the invention, a semiconductor memory apparatus has:
at least one first and one second memory bank, which each have a large number of row and column lines and at least one redundant column line,
an activation device, which is designed for activation of the redundant column lines as replacement lines for defective column lines, and has a large number of programmable addressing fuses (column redundancy fuses) and at least one programmable selection fuse (enable fuse) with at least two electrical selection fuse states,
with the selection fuse being designed such that at least one of the addressing fuses in the first selection fuse state is electrically associated with the first memory bank and in the second selection fuse state is electrically associated with the second memory bank, in order to activate the respective redundant column line.
The invention proposes that two memory banks in the semiconductor memory apparatus according to the invention have the capability to xe2x80x9cdivide upxe2x80x9d the addressing fuses that are provided. The at least one selection fuse is provided in the activation device for this purpose, via which an addressing fuse can be associated with either the first memory bank or the second memory bank. Existing addressing fuses can thus be used both in conjunction with the first memory bank and in conjunction with the second memory bank.
In conventional semiconductor memory apparatuses, no such selectable association is possible between addressing fuses and either the first or the second memory bank. Instead of this, conventional semiconductor memory apparatuses with a number of memory banks each have addressing fuses which are permanently associated with specific memory banks. In consequence, in known semiconductor memory apparatuses, one addressing fuse can be used only in conjunction with a memory bank which is permanently associated with it.
The semiconductor memory apparatus according to the invention in contrast has greater repair flexibility while having the same number of fuses, so that the production yield of such components can be increased. In other words, in comparison to a conventional semiconductor memory apparatus, fewer addressing fuses need to be provided in the semiconductor memory apparatus according to the invention, for a predetermined maximum number of possible repair options, so that the chip size of the semiconductor memory apparatus according to the invention can be reduced in comparison to that of the conventional semiconductor memory apparatus. Equally, it is possible to use the selection fuse to associate the at least one addressing fuse with any given memory bank, when more than two memory banks are provided in the semiconductor memory apparatus.
According to one preferred embodiment, the first selection fuse state corresponds to an electrically nonconductive state, and the second selection fuse state corresponds to an electrically conductive state. The programming of the selection fuse, which is thus equivalent to (reversible or irreversible) fixing of the selection fuse state, thus includes fixing of this state as a nonconductive state or as a conductive state. However, it is equally possible to associate a conductive state with the first selection fuse state, and a nonconductive state with the second selection fuse state.
According to one particularly preferred embodiment, at least one first and one second selection fuse are provided, with at least one of the addressing fuses being associated with the first memory bank when the first selection fuse is in the first selection fuse state and the second selection fuse is in the second selection fuse state. In contrast, this addressing fuse is then associated with the second memory bank when the first selection fuse is in the second selection fuse state and the second selection fuse is in the first selection fuse state,
The association or fixing of the at least one addressing fuse with the first or the second memory bank is accordingly preferably carried out by means of two selection fuses. If the first selection fuse is in the first selection fuse state (for example an electrically nonconductive state) and the second selection fuse is in the second selection fuse state (for example an electrically conductive state), then the at least one addressing fuse is associated with the first memory bank. Programming of the addressing fuse can thus be used to repair a faulty column line in the first memory bank, by using a redundant column line, which is provided in the first memory bank, to replace this faulty column line. If the selection fuse states are interchanged in comparison to the state described above, then the addressing fuse is associated with the second memory bank.
The addressing fuses and/or the selection fuses are preferably fuses which can be blown by laser and/or electrically. Such a fuse which can be blown by laser allows (irreversible) programming, that is to say fixing of the fuse state, in which a focused laser beam interrupts, for example, a metal track in the fuse. Electrically programmable fuses can be changed to a specific fuse state irreversibly, or reversibly by applying an electrical voltage to the fuse. Such electrically programmable fuses may, for example, have a construction such as that which is known from PROM memory concepts.
According to a further preferred embodiment, the at least one selection fuse is designed for electrical association of one group of the addressing fuses with one of the memory banks. The selection fuse can thus be programmed to electrically associate an entire group of addressing fuses with either the first memory bank or the second memory bank.
The large number of addressing fuses preferably forms an addressing fuse bank. Such an addressing fuse bank may preferably include a number of groups of addressing fuses, for example arranged linearly, in which case each such group can be programmed as a function of an electrical address of a defective column line in one of the memory banks. While, in the case of conventional semiconductor memory apparatuses with a repair capability, a dedicated addressing fuse bank had to be provided for each memory bank and was permanently associated with this memory bank, the invention makes it possible to use only a single addressing fuse bank. It is possible to use the at least one selection fuse to decide whether the addressing fuse bank or a group of the addressing fuses in this bank should be associated with the first or the second memory bank. The addressing fuse bank is preferably arranged between the memory banks. This allows the semiconductor memory apparatus to be designed in a space-saving manner.
According to one preferred embodiment, each of the memory banks has a large number of redundant column lines. In comparison to the addressing fuses and selection fuses, the redundant column lines in the memory banks occupy relatively little chip surface area. It is thus possible to provide a large number of redundant column lines in each memory bank without having to significantly enlarge the semiconductor memory apparatus. The minimum necessary chip surface area for a semiconductor memory apparatus with a repair capability, in comparison to such an apparatus without a repair capability, is accordingly not governed by the additional redundant column lines, but primarily by the fuses that are additionally required. It has been found to be advantageous to arrange the column lines such that they are distributed in the memory banks,
According to one particularly preferred embodiment, the memory banks are DRAM memory banks, in particular SDRAM memory banks.
According to the invention, a repair method for a semiconductor memory apparatus comprises the following steps:
provision of the semiconductor memory apparatus with at least one first and one second memory bank, which each have a large number of row and column lines and at least one redundant column line, with the semiconductor apparatus having an activation device which is designed for activation of the redundant column line as a replacement line for a defective column line;
identification of a memory bank number of that memory bank which has the defective column line;
identification of an electrical address for the faulty column line;
programming of at least one addressing fuse of the activation device as a function of the identified address;
programming of at least one selection fuse of the activation device as a function of the identified memory bank number;
with the programming of the selection fuse electrically associating the addressing fuse with the memory bank with the identified memory bank number, so that the faulty column line is replaced by the redundant column line.
Accordingly, in the method according to the invention, the semiconductor memory apparatus is first of all checked for any faulty column lines. If such a column line has been found, then the method identifies the memory bank in which the faulty column line is located, and which electrical address is associated with it. This information is then used to program the activation device in a suitable manner. The programming is carried out by fixing (irreversibly or reversibly) the states of addressing and selection fuses. The address information for the faulty column line is used for programming the addressing fuse or the addressing fuses, so that, when the memory cell array is subsequently accessed, the faulty column line is not addressed but rather a redundant column line which replaces it.
Since the addressing fuse or the addressing fuses may be associated with both the first memory bank and the second memory bank, it is necessary to determine by programming of the at least one selection fuse the memory bank for which the programmed addressing fuses are intended to be used. The at least one selection fuse is thus programmed as a function of the memory bank number which contains the faulty column line. Programming of the fuses is equivalent to fixing the fuse state, for example by blowing a fuse by means of a laser. The programming of the intended selection fuse advantageously makes it possible for the first and the second memory bank to xe2x80x9csharexe2x80x9d at least one addressing fuse. It is thus possible to reduce the required total number of addressing fuses for a predetermined number of repair options. According to one preferred embodiment of the repair method according to the invention, one group of addressing fuses is programmed as a function of the identified address, with the group in the memory bank being electrically associated with the identified memory bank number by programming of the at least one selection fuse. It is thus possible to electrically associate an entire group of addressing fuses with either the first memory bank or the second memory bank, by programming one selection fuse.
The addressing fuses and/or selection fuses are preferably programmed electrically and/or by means of a laser.